Frequency Agile Wideband Phase Lock Loops for RF-FPGAs
نویسندگان
چکیده
This project develops PLL macros that use novel digital architectures to achieve a user configurable optimum balance between phase noise, frequency resolution, frequency switching time, and power consumption. The PLL macros are implemented in SiGe BiCMOS to take advantage of the good phase noise and power consumption attributes. The digital nature of the implementation facilitates easy porting to more aggressively scaled processes.
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